1. Field of the Invention
This invention relates to the field of semiconductor devices, and more specifically, to a process for reducing silicide resistivity.
2. Background Information
In the manufacture of semiconductor devices it has become increasingly more important to develop devices that are smaller and more dense while increasing the speed and performance of such devices. Speed of the devices, for example transistors, often depend upon the polysilicon gate electrodes. The size, thickness, length, and material making up the gate electrode all affect the speed of the transistor in one way or another.
Tungsten silicide (WSi2) is a material that has been used in the manufacture of gate electrodes in semiconductor devices, for example DRAM devices. Tungsten silicide is used to reduce the line resistance in polysilicon gate structures. Reducing the line resistance decreases the switching time of the transistor and thereby increases the speed of the transistor.
Most manufacturers use a standard approach to the formation of the tungsten silicide gate electrode. First, a thin gate oxide layer 110 is formed on a substrate 100, as illustrated in FIG. 1a. Then a layer of polysilicon 120 is deposited on thin gate oxide layer 110, as illustrated in FIG. 1b. Next a layer of tungsten silicide 130 is deposited on the polysilicon layer 120, as illustrated in FIG. 1c. An anneal is performed in order to improve the surface quality of the tungsten silicide layer 130. Finally, the tungsten silicide layer 130, the polysilicon layer 120, and gate oxide layer 110 are all patterned into a gate electrode 140 using well known photolithographic patterning techniques, as illustrated in FIG. 1d. It should be noted that photolithographic patterning techniques are well known in the art and are therefore not discussed in detail herein.
By using the above described standard approach for forming tungsten silicide on a polysilicon gate, manufacturers are able to produce gate electrodes with resistivities as low as approximately 17 micro-ohm per centimeter (xcexc-ohm/cm). Such gate electrode resistivities increase the speed of the transistors, however, faster and faster devices are needed in order to keep up with current trends in the industry.
Thus, what is needed is a method and apparatus that decreases the resistivity in gate electrodes further, thereby increasing the speed of the semiconductor device.
A method for reducing the resistivity in a gate electrode is described. A silicon layer is formed on a substrate. A tungsten silicide layer is then formed on the silicon layer. The tungsten silicide layer is implanted with boron ions and an anneal is performed. The tungsten silicide layer and silicon layer are then patterned to form a gate electrode.
Additional features and benefits of the present invention will become apparent from the detailed description, figures, and claims set forth below.